Detailed Explanation of Chip Manufacturing Process and Hardware Cost
Chips (IC) in electronics are a way to miniaturize the circuit and are often manufactured on the surface of a semiconductor wafer. It is also a way of miniaturizing circuits in electronics, mainly including semiconductor equipment, but also passive components, etc., and is usually manufactured on the surface of a semiconductor wafer.
The aforementioned integrated circuit we manufactured on the surface of a semiconductor chip has another name thin film integrated circuit; a substrate or circuit board integrate the independent semiconductor devices and passive components. They constitute another thick-film hybrid integrated circuit is a miniaturized circuit.
The characteristic of the integrated circuit industry is that the winner takes all. Giants like Intel can make as much as 60% of their profits during their peak period. So, what is the actual cost of a CPU that costs hundreds or thousands of dollars?
Let’s take a look at the manufacturing process first
The complete chip manufacturing process includes several links such as chip design, wafer manufacturing, packaging manufacturing, and cost testing, among which the wafer manufacturing process is particularly complex. The manufacturing process of precision chips is very complicated. First of all, the chip design is the “pattern” generated according to the needs of the design.
The raw material wafer of the chip
The composition of the wafer is silicon. Silicon is refined from quartz sand. The wafer is purified by silicon element (99.999%). Then some pure silicon is made into silicon ingots, which become the quartz semiconductor for manufacturing integrated circuits. Material, slicing it is the wafer specifically required for chip production. The thinner the wafer, the lower the production cost, but the higher the process requirements.
Wafer coating
It can resist oxidation and temperature resistance, and its material is a kind of photoresist.
Wafer photolithography development and etching
This process uses chemicals that are sensitive to ultraviolet light, which becomes soft when exposed to ultraviolet light. controlling the position of the shading object can obtain the shape of the chip. a photoresist coats the silicon wafer. So that it will dissolve under ultraviolet light. At this time, the part directly irradiated by ultraviolet light can dissolve the first shade, and then we wash away that part with a solvent. This way the rest is the same shape as the shade, and this effect is exactly what we want. In this way, the silicon dioxide layer we need is obtained.
Add impurities
We implanted lons in the wafer to generate corresponding P and N semiconductors. The specific process is to start from the exposed area on the silicon wafer and put it into the chemical ion mixture.
This process will change the conduction mode of the doped area so that each transistor can be turned on, off, or carry data. Simple chips can use only one layer, but complex chips usually have many layers. At this time, this process is repeated continuously, and different layers can be connected through an open window. This is similar to the manufacturing principle of multilayer PCB boards. More complex chips may require multiple silicon dioxide layers, repeating photolithography and the above process to form a three-dimensional structure can achieve this.
Wafer test
After the above several processes, wafer forms thelattice-shaped crystal grains. needle testing test the electrical characteristics of each die. Generally, the number of crystal grains is huge, and it is a very complicated process to organize a needle test mode. This requires mass production of models with the same chip specifications and structures as much as possible during production. The larger the quantity, the lower the relative cost, which is also a factor why mainstream chip devices are low in cost.
Package
we fix the finished wafer, we bound the pins, and we make various packaging according to requirements. This is the reason why the same chip core can have different packaging forms. For example: DIP, QFP, PLCC, QFN, etc. external factors determine this mainly, such as the user’s application habits, application environment, and market form.
Testing and packaging
After the above-mentioned process flow, we complete the chip production. This step is to test the chip, reject defective products, and package.
The hardware cost structure of the chip
The cost of the chip includes the hardware cost of the chip and the design cost of the chip.
Introduction to hardware cost?
The cost of chip hardware includes four parts: chip cost + mask cost + test cost + packaging cost (IC design companies in the ARM camp have to pay ARM design and development fees and royalties for each chip, but the author mainly describes the independent CPU and Intel. The giants will save the cost of purchasing IP), and also remove the waste of test packaging.
Expressed as a formula:
Chip hardware cost = (wafer cost + test cost + packaging cost + mask cost) / final yield
Let me give a simple explanation of the above names to make it easier to understand.
The definition of wafer
Wafer is the raw material for manufacturing chips, and the cost of the chip is the same as the cost of the material (silicon wafer) that each chip use. Under normal circumstances, especially if the output is large enough, and with independent intellectual property rights, if we calculate the mass production in units of 100 million, the cost of the chip accounts for the highest proportion. However, there are exceptions. In the following package cost, we will introduce a strange example.
Meaning of packaging
Packaging is the stacking of substrates, cores, and heat sinks to form the CPU that everyone sees daily. This process required packaging cost. In the general case of huge output, the packaging cost generally accounts for about 5%-25% of the hardware cost, but some of IBM’s chip packaging costs account for about half of the total cost, and somebody said that the highest has reached 70%.
The test can identify the key characteristics of each processor, such as the highest frequency, power consumption, heat generation, etc., and determine the level of the processor, such as classifying a bunch of chips into: I5 4460, I5 4590, I5 4690, I5 4690K After that, Intel can offer different prices according to different grades. However, we can ignore the test cost if the chip output is large enough.
Adopting different process technologies requires Mask cost. For example, the 28nm SOI process is 4 million US dollars ; 28nm HKMG costs 6 million US dollars.
However, at the beginning of the advent of advanced process technology, the cost was quite expensive-when the 14nm process first appeared in 2014, its mask cost was 300 million US dollars (with the passage of time and TSMC, Samsung mastered 14/16nm Process, the current price should not be so expensive); and Intel is developing a 10nm process. According to Intel official estimates, the cost of the mask needs at least $1 billion.
On the other hand, this reflects why giants use most advanced and expensive process technology still earns a lot.This is why IC design has a winner-takes-all feature.
test costs, packaging costs, and mask costs include the cost of photolithography, etching, metal deposition, level testing, etc. steps. And the cost of that foundries spent, as well as photolithography machines, etching machines, and flip-chips. Therefore, there is no need to calculate them separately.
Chip cost
Since we cannnot guarantee 100% utilization when processing and dicing wafers into wafers, there is a yield problem, so we can express the cost of wafers in this formula:
The cost of the chip = the cost of the wafer / (the number of chips per wafer * chip yield)
Since the wafer is round and the wafer is rectangular, somebody will inevitably waste leftover materials.
The number of chips per wafer = (wafer area/chip area)-(wafer circumference/(2*chip area) square root)
The yield rate of the wafer is closely related to the process complexity and the number of defects per unit area. The company express the yield rate of the wafer as:
Yield rate of wafer = (1+B*cost of wafer/A) (-A power)
A is the process complexity. For example, the complexity of an autonomous CPU-X using a 40nm low-power process is between 2 and 3;
B is the number of defects per unit area, and the number of defects per unit area of the autonomous CPU-X using a 40nm process is between 0.4 and 0.6.
Assuming that the length of the autonomous CPU-X is about 15.8mm and the width is about 12.8mm, (the aspect ratio is 37:30, it is not easy to control the aspect ratio of a quad-core chip at this ratio) and the area is about 200 square millimeters (for It is convenient to calculate and remove the fraction). A 12-inch wafer is about 70,000 square millimeters, so a wafer can hold 299 autonomous CPU-X.In the formula for the wafer yield rate, take a=3 and b=0.5 into the calculation, and the wafer yield rate is 49%, which means that a 12-inch wafer can produce 146 good chips, and the price of a 12-inch wafer is US$4,000, each chip cost US$28.
Chip hardware cost calculation
There is no specific formula for the cost of packaging and testing. However, the cost of testing is roughly proportional to the square of the number of pins. And the cost of packaging is roughly proportional to the power of the pins multiplied by the third power. If CPU-X adopts the independent chip of 40nm low power consumption craft, its test cost is about 2 dollars, the packaging cost is about 6 dollars.
Since the mask cost of the 40nm low-power process is US$2 million, if the sales volume of the independent CPU-X reaches 100,000, the mask cost is US$20, test cost = US$2, packaging cost = US$6, chip cost = 28 dollars into the formula, the chip hardware cost = (20+2+6)/0.49+28=85 dollars
The hardware cost of the autonomous CPU-X is $85.
If the autonomous CPU-Y adopts 28nm SOI process and the chip area is about 140 square millimeters, can cut into 495 CPUs. Because 28nm and 40nm processes are both very mature technologies, the impact of cutting costs is minimal. So we can calculate the wafer price at US$40 million, and we calculate the wafer yield rate at 49%. A 12-inch wafer can cut 242 wafers, and the cost of each wafer is US$16.
If the output of the autonomous CPU-X is 100,000, the mask cost is 40 US dollars. According to the calculation of packaging and testing about 20% of the total chip cost and the wafer yield rate of 49%, the hardware cost of the chip is 122 US dollars.
If the output of the independent chip is 1 million, the cost of the mask is US$4. According to the packaging test, which accounts for about 20% of the total cost, the final yield rate is 49%. The hardware cost is US$30. If the output of the independent chip is 10 million, the cost of the mask will be US$0.4. According to the package and test , the final yield rate is 49%. And the hardware cost of the chip is US$21.
Obviously, under the same output, the use of more advanced process technology will increase the cost of chip hardware. When the output is large enough, the huge amount can shares the original high cost. Also, it can reduced the cost of the chip greatly.
Chip pricing
The hardware cost is relatively clear, but the design cost is more complicated. This includes the salary of the engineer, the cost of development tools. If it is an independent CPU, it is okay (a certain independent microstructure can do without third-party IP). If it is an IC design company in the ARM camp, we need a large amount of outsourcing IP. But the price of these IPs it is expensive. So it is not easy to quantify the design costs of various IC design companies at home and abroad.
When the hardware cost is 8, the price is 20. And we price the independent CPU-X at $212 when the output is 100,000 pieces. Don’t think this price is high, it’s actually very low. Intel’s general pricing strategy is 8:35, and AMD’s history has reached 8:50.
we can see that to reduce the cost/selling price of the CPU, the output is the utmost importance. This is also the key to Intel and Apple’s ability to use relatively expensive manufacturing processes and capture excess profits.
