Introduction of an Application Specific Integrated Circuit (ASIC)

A collection of electrical circuits on a single small flat piece (or “chip”) of semiconductor material, commonly silicon, is known as an integrated circuit (IC). Modern integrated circuits are extremely sophisticated, with millions of transistors packed onto a single chip.

Different types of ICs exist based on their design process, adaptability, and applications:

Standard integrated circuits

ASIC is an acronym for the American Society for Industrial (Application Specific Integrated Circuits)

ASSP is an acronym for “Associate (Application Specific Standard Products)

Because ASICs are the topic of this essay, we’ll separate them into two categories: ASICs and non-ASICs. ASICs and their many varieties will be discussed here.

What Is an Application Specific Integrated Circuit?

ASIC stands for application-specific integrated circuit. It is a non-standard integrated circuit that is built for a specific usage or application. ASICs are often intended for products with a high production run and contain a significant portion of the electronics required on a single integrated circuit. As a result, the cost of an ASIC design (for example, NRE) is relatively expensive, and ASICs are often employed for large-volume devices.

Despite the high design cost of ASICs, they can be cost effective for many high-volume applications, especially when a considerable portion of a large system can be incorporated into a single ASIC circuit, reducing the number of external components dramatically. By decreasing the size of electrical goods and increasing the density of logic gates per chip, ASIC contributed to transform technology. Intel’s CPU or a bitcoin ASIC are two instances of ASIC. ASIC design may be done in two ways:

Design that is semi-custom

Completely unique design

Semi-custom design is categorized into a few categories.

Different Types of ASICs

Full-custom ASICs

Some or all of the mask layers are modified in full-custom ASICs. This sort of ASIC typically takes 8 weeks to produce (of course, this does not include the design time).

When there are no suitable libraries or when current libraries are not fast enough, full-custom ASICs are required.

The available pre-designed cells use more energy than is permitted.

The available cell space is too huge, or the technology is new, and there are no libraries yet.

The following are some of the benefits of Full-custom ASICs:

Manufacturing is the most cost-effective option (since have smaller area)

Provide the fastest service possible.

They do, however, have drawbacks, some of which are listed below:

Complexity has increased.

Design timeframes have been longer.

Design costs are higher, and the risks are higher.

Full-custom design process is utilized to create standard library cells used in Semi-custom Standard-Cell based ASIC design. They provide the same level of performance and flexibility while cutting down on time and danger. During the design of S Standard-Cell based ASICs, the ASIC designer just specifies the location of standard cells.

The following concepts guide the creation of flexible blocks in CBIC:

Standard cells are constructed similarly to little bricks in a wall.

For constructing rows, standard cell groups fit horizontally.

Flexible blocks are made by stacking rows vertically and then reshaping them during the design process.

Other conventional cell blocks or whole custom blocks are attached to flexible blocks.

Semi-Custom ASICs

Standard-Cell based ASICs (CBICs) are the first type of Semi-Custom ASIC. They use pre-designed logic cells known as standard cells. Because they are the most popular, when we mention ASIC, we typically mean this sort of ASIC. Logic cells from the following sources are utilized to create this sort of ASIC:

Cell libraries that are commonly used

Mega-cells are a type of cell that has a lot (Microcontroller or Microprocessor for example)

Blocks that are completely customized

Macros at the System Level (SLMs)

Cores, Functional Standard Blocks (FSBs), and so on.

All mask layers (transistors and connections) are modified in this form of Semi-Custom ASIC (CBIC). Typically, the manufacturing process takes 8 weeks. Custom blocks can be put in this sort of ASIC. They, like other types of ASICs, have benefits and drawbacks. The following are some of the benefits:

Time, money, and danger are all saved.

Individual standard cells can be tuned for area, power, or speed.

The following are some of the drawbacks of this sort of ASIC:

A conventional cell library requires a lot of effort and money to create.

For the new design, the fabrication time for all layers of the chip has increased.

Gate Array based ASIC

rdc 800 Transistors are developed and produced on a silicon wafer in a gate array-based ASIC, but interconnects are not. On a gate array, a base array is a specified design of transistors.

The base cell is the smallest piece that is repeated in a forma gate array. Custom masks can only be used to define the first few layers of metal interconnects that define the interconnect between transistors. This is known as a masked gate array (MGA). The turnaround time for this sort of ASIC is normally a few days to a few weeks.

A gate array, also known as a masked gate array or a pre-defined gate array, is a type of array that employs books (macros) to reduce turnaround time and consists of a basic array built of. A basal cell or a primordial cell. Gate arrays are divided into three categories: Channeled gate arrays, Channelless gate arrays and Structured gate arrays.

The connection is only modified in the channeled gate array and uses pre-defined spacing between rows of base cells. The manufacturing lead time is anywhere from two days to two weeks. This is similar to CBIC, except unlike CBIC, the space is fixed here.

Channeled Gate Arrays

Only a few (the top few) mask layers (interconnect) are modified in a channelless gate array, also known as a channel free gate array, a sea-of-gates array, or a SOG array. The manufacturing lead time is anywhere from two days to two weeks.

The presence of a pecific area for connecting is the primary benefit of channeled gate arrays.

The most significant disadvantage of this form of array is that, unlike CBIC space, it is not feasible to alter it.

Channelless Gate Arrays

The following are the main distinctions between a channelless gate array and a channeled gate array:

On a channelless gate array, there are no designated spaces for routing between cells.

In a channelless array, we utilize a region of transistors for routing but do not create any connections to the devices beneath; we just leave the transistors unused.

The logic density — the amount of logic that can be implemented in a given silicon area – is higher for channelless gate arrays.

A channelless gate array’s connect mask can be changed, whereas a channeled gate array’s connect mask is rarely altered. In channelless structures, this results in denser cells.

Structured Gate Arrays

The properties of CBICs and MGAs are combined in a structured gate array.

The fixed gate-array base cell is one of the MGA’s main drawbacks. This makes memory implementation inefficient or complicated, for example.

Only the connection is customized in a structured gate array, also known as an embedded gate array, masterslice, or masterimage, and bespoke blocks (the same for each design) can be integrated. Manufacturing can take anywhere from two days to two weeks.

In an embedded gate array, a portion of the IC is set aside for a certain purpose.

Conclusion

In conclusion, an application-specific integrated circuit (ASIC) is designed to perform a particular function or a group of related functions.